EDA智能四路抢答器设计(框图+vhdl源程序+仿真图) 第4页
ENTITY JFQ IS
PORT(RST: IN STD_LOGIC;
ADD: IN STD_LOGIC;
CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
AA2,AA1,AA0,BB2,BB1,BB0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CC2,CC1,CC0,DD2,DD1,DD0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY JFQ ;
ARCHITECTURE ART OF JFQ IS
BEGIN
PROCESS(RST,ADD,CHOS) IS
VARIABLE POINTS_A2,POINTS_A1: STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE POINTS_B2,POINTS_B1: STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE POINTS_C2,POINTS_C1: STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE POINTS_D2,POINTS_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF (ADD'EVENT AND ADD='1') THEN
IF RST='1' THEN--复位
POINTS_A2: ="0001"; POINTS_A1: ="0000";
POINTS_B2: ="0001"; POINTS_B1: ="0000";
POINTS_C2: ="0001"; POINTS_C1: ="0000";
POINTS_D2: ="0001"; POINTS_D1: ="0000";
ELSIF CHOS="0001" THEN--A回答正确，加10分
IF POINTS_A1="1001" THEN
POINTS_A1: ="0000";
IF POINTS_A2="1001" THEN
POINTS_A2: ="0000";
ELSE
POINTS_A2: =POINTS_A2+'1';
END IF;
ELSE
POINTS_A1: =POINTS_A1+'1';
END IF;
ELSIF CHOS="0010" THEN--B回答正确，加10分
IF POINTS_B1="1001" THEN
POINTS_B1: ="0000";
IF POINTS_B2="1001" THEN
POINTS_B2: ="0000";
ELSE
POINTS_B2: =POINTS_B2+'1';
END IF;
ELSE
POINTS_B1: =POINTS_B1+'1';
END IF;
ELSIF CHOS="0100" THEN--C回答正确，加10分
IF POINTS_C1="1001" THEN
POINTS_C1: ="0000";
IF POINTS_C2="1001" THEN
POINTS_C2: ="0000";
ELSE
POINTS_C2: =POINTS_C2+'1';
END IF;
ELSE
POINTS_C1: =POINTS_C1+'1';
END IF;
ELSIF CHOS="1000" THEN--D回答正确，加10分
IF POINTS_D1="1001" THEN
POINTS_D1: ="0000";
IF POINTS_D2="1001" THEN
POINTS_D2: ="0000";
ELSE
POINTS_D2: =POINTS_D2+'1';
END IF;
ELSE
POINTS_D1: =POINTS_D1+'1';
END IF;
END IF;
END IF;
AA2<=POINTS_A2; AA1<=POINTS_A1; AA0<="0000";
BB2<=POINTS_B2; BB1<=POINTS_B1; BB0<="0000";
CC2<=POINTS_C2; CC1<=POINTS_C1; CC0<="0000";
DD2<=POINTS_D2; DD1<=POINTS_D1; DD0<="0000";
END PROCESS;
END ARCHITECTURE ART;
4.3.3 计时器电路JSQ的VHDL源程序
--JSQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JSQ IS
PORT(CLR,LDN,EN,CLK: IN STD_LOGIC;
毕业论文http://www.751com.cn/ 论文网http://www.lwfree.com/OF JSQ IS
SIGNAL DA: STD_LOGIC_VECTOR(3 DOWNTO 0); --信号DA,调整时间的个位数
SIGNAL DB: STD_LOGIC_VECTOR(3 DOWNTO 0); --信号DB，调整时间的十位数
BEGIN
PROCESS(TA,TB,CLR) IS
BEGIN
IF CLR='1' THEN--清零
DA<="0000";
DB<="0000";
ELSE
IF TA='1' THEN--调整时间的个位数