制作一个以fpga/cpld为核心的数字系统 第2页
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity lled is
port(clk:in std_logic;
st:in std_logic;
stout :out std_logic;
    
 dout:out std_logic_vector(6 downto 0)
     );
end lled;

architecture hav of lled is
signal q:std_logic_vector(6 downto 0);
signal d:std_logic_vector(3 downto 0);
signal streg:std_logic;
begin
stout<= not streg;
process(st)
begin
if st'event and st='1' then
streg<= not streg;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if streg='1' then
 if d="1001" then
  d<="0000";
 
 else d<=d+1;
751com.cn

 end if;
end if;
end if;
end process;
with d select
q<="1000000" when "0000",
   "1111001" when "0001",
   "0100100" when "0010",
   "0110000" when "0011",
   "0011001" when "0100",
   "0010010" when "0101",
   "0000010" when "0110",
 "1111000" when "0111",
 "0000000" when "1000",
    "0010000" when others;
dout<=q;end hav; 

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