基于VHDL语言的FIR滤波器设计 第8页
附录
分频器程序：
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_unSIGNED.ALL;
entity ad is
port(
a:in std_logic;
--c:out std_logic_vector(7 downto 0);
b:out std_logic;
c:out std_logic
);
end ad;
architecture ab of ad is
signal x:integer range 0 to 6;
signal mid:std_logic;
begin
process(a)
begin
if a'event and a='1' then
if x=2 then
x<=0;
mid<=not mid;
else
x<=x+1;
end if;
b<=mid;
c<=mid;
end if;
end process;
end ab;
乘累加模块程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package pre is
constant inb: positive:=8;
constant hb: positive:=8;
constant mres:positive:=inb+hb;
constant outb:positive:=mres+3;
constant h0:std_logic_vector:="00000011";
constant h1:std_logic_vector:="00011000";
constant h2:std_logic_vector:="00101010";
constant h3:std_logic_vector:="00111001";
constant h4:std_logic_vector:="00111001";
constant h5:std_logic_vector:="00101010";
constant h6:std_logic_vector:="00011000";
constant h7:std_logic_vector:="00000011";
type regs is array(1 to 7) of std_logic_vector(inb-1 downto 0);
end pre;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pre.all;
entity fir is
port(xin:in std_logic_vector(inb-1 downto 0);
clk:in std_logic;
outs:out std_logic_vector(15 downto 0));
end fir;
architecture rtl of fir is
signal ir:regs;
signal m0,m1,m2,m3,m4,m5,m6,m7:std_logic_vector(15 downto 0);
signal a0,a1,a2,a3:std_logic_vector(15 downto 0);
signal b0,b1,b2:std_logic_vector(15 downto 0);
--signal c0,c1:std_logic_vector(15 downto 0);
begin
process(clk)
begin
if clk'event and clk='1'then
m0<=xin*h0;
m1<=ir(1)*h1;
m2<=ir(2)*h2;
m3<=ir(3)*h3;
m4<=ir(4)*h4;
m5<=ir(5)*h5;
m6<=ir(6)*h6;
m7<=ir(7)*h7;
for i in 0 to 5 loop
ir(7-i)<=ir(6-i);
end loop;
ir(1)<=xin;
a0<=m0+m7;
a1<=m1+m6;
a2<=m2+m5;
a3<=m3+m4;
b0<=a0+a1;
b1<=a2+a3;
outs<=b0+b1;
end if;
end process;
end rtl;
进制转换模块程序：
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_unSIGNED.ALL;
entity zhuan is
port(
A: in std_logic_vector(14 downto 0);
y: out std_logic_vector(19 downto 0));
end zhuan;
architecture one of zhuan is
begin
process(a)
variable d: std_logic_vector(19 downto 0);
variable z: std_logic_vector(14 downto 0);
begin
z:=a;
if z>=30000 then d(19 downto 16):="0011"; z:=z-30000;
elsif z>=20000 then d(19 downto 16):="0010"; z:=z-20000;
elsif z>=10000 then d(19 downto 16):="0001"; z:=z-10000;
else d(19 downto 16):="0000";
end if;
if z>=9000 then d(15 downto 12):="1001"; z:=z-9000;
elsif z>=7000 then d(15 downto 12):="0111"; z:=z-7000;
elsif z>=6000 then d(15 downto 12):="0110"; z:=z-6000;
elsif z>=5000 then d(15 downto 12):="0101"; z:=z-5000;
elsif z>=4000 then d(15 downto 12):="0100"; z:=z-4000;
elsif z>=3000 then d(15 downto 12):="0011"; z:=z-3000;
elsif z>=2000 then d(15 downto 12):="0010"; z:=z-2000;
elsif z>=1000 then d(15 downto 12):="0001"; z:=z-1000;
else d(15 downto 12):="0000";
end if;
if z>=900 then d(11 downto 8):="1001"; z:=z-900;
elsif z>=800 then d(11 downto 8):="1000"; z:=z-800;
elsif z>=700 then d(11 downto 8):="0111"; z:=z-700;
elsif z>=600 then d(11 downto 8):="0110"; z:=z-600;
elsif z>=500 then d(11 downto 8):="0101"; z:=z-500;
elsif z>=400 then d(11 downto 8):="0100"; z:=z-400;
elsif z>=300 then d(11 downto 8):="0011"; z:=z-300;
elsif z>=200 then d(11 downto 8):="0010"; z:=z-200;
else d(11 downto 8):="0000";
end if;
if z>=90 then d(7 downto 4):="1001"; z:=z-90;
elsif z>=80 then d(7 downto 4):="1000"; z:=z-80;
elsif z>=70 then d(7 downto 4):="0111"; z:=z-70;
elsif z>=60 then d(7 downto 4):="0110"; z:=z-60;
elsif z>=50 then d(7 downto 4):="0101"; z:=z-50;
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